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Study on Area Efficient Radix-2 FFT Architecture to Process Twin Data Streams for High Speed Real Time Application

IJEECC Front Page
Author(s):
Anupriya K.P, Rachana M.K, Manju V.M
Volume
4, Issue 1
Pages:
638-643
Year of Publication:
June, 2017
Indian Journal of Emerging Electronics in Computer Communications-IJEECC
ISSN:
2393-8366
Citation: Anupriya K.P, Rachana M.K, Manju V.M."Study on Area Efficient Radix-2 FFT Architecture to Process Twin Data Streams for High Speed Real Time Application." Indian Journal of Emerging Electronics in Computer Communications,4.1(2017):638-643.
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Abstract:
This paper proposes a novel shared multiplier scheduling scheme for area efficient radix-2 FFT architecture to process twin data streams for High speed real time application. In these days many application require simultaneous computation of multiple independent Fast Fourier Transform with its outputs are in natural order. So this paper present a 16 point pipelined FFT processor for FFT computation of two independent data stream. In this N/2 decimation in time FFT and N/2 point decimation in frequency FFT to process the odd and even samples of two data streams separately. This SMSS technique reduce total number of complex multiplier and hardware complexity. The proposed pipelined FFT processor based on SMSS are designed using XILINX ISE TOOL and coded by Verilog HDL language. In addition the proposed processor can be extended to any FFT sizes using additional stages.
Keywords:SMSS, Radix 2 pipelined FFT, DIT and DIF, Multipath delay commutator, Odd and Even samples, MIMO, Xilinx ISE Tool.

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