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Thermal-Effects of Power-Aware Test Vector Reordering

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Low power digital testing approaches target the minimization of overall switching activity. This may lead to non-uniformity in the spatial power distribution which may cause localized heating and lead to an appreciable temperature difference across the layout of the circuit. Temperature is a function of power density. With increasing chip density, power aware testing will prove inadequate and has to be replaced by thermal aware testing strategies. Most of the efficient low power testing algorithms use vector reordering scheme. In this paper we investigate the influence of power aware test vector ordering technique on peak temperature and temperature distribution within the chip. Effectiveness of the approaches has been established via thermal simulation of ISCAS89 benchmark circuits. The proposed scheme outperform existing test pattern reordering techniques that target minimization of either total power (and thus heat) or peak temperature.
Keywords:Low Power Testing, Thermal Aware Testing, Vector Reordering..


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