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High Speed 16 Bit Vedic MultiplierArchitecture using Modified Carry SelectAdder

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Abstract:
Multiplication is a complex operation that introduces high delay and require large area for multiplier design. In this paper, a high speed and area efficient 16x16 Vedic Multiplier is designed by using high speed modified carry select adder. Modified carry select adder is faster than other conventional adder structures. Vedic multiplication has been introduced, which is different from other multiplication by shift and addition operations. This paper presents a new design methodology for less delay and area efficient Multiplier based up on aVedic Mathematic techniques. Vedic multiplier is based on the crosswise and vertical algorithm.The comparison of delay and area of multipliers with different adder architectures has been made to prove its efficiency. The performance analysis shows that the proposed architecture makes advantages in terms of delay and area. The design simulation is done in ModelSimPe 5.5using verilog hardware description language. It is synthesized by using Xilinx ISE14,2.
Keywords:Ripple carry adder (RCA), Carry select adder (CSA).

References:

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