SLGP Header

Low cost all digital duty cycle corrector

IJEECC Front Page

A system clock with a 50% duty cycle is demanded in high-speed data communication applications, such as double data rate memories and double sampling analog-to-digital converters. In this paper, low-cost all-digital duty-cycle corrector (ADDCC) is presented. The proposed ADDCC uses a delay-recycled half-cycle time delay line to reduce the required length of the delay line to half of the input clock period. Thus, it can extend the operating frequency toward a lower frequency with small area cost as compared with the conventional design. The proposed design is implemented in a standard performance 250nm CMOS process, and the active area is 170 × 170 μm2. The input frequency of the proposed ADDCC ranges from 75 to 734 MHz, and the input duty-cycleranges from 9% to 86%. The measured output duty-cycle error is less than 1.78%. The proposed ADDCC consumes 4.59 mW at 734 MHz and 0.9 mW at 75 MHz with a 2.5.0-V power supply.
Keywords:All-digital duty-cycle corrector (ADDCC), Half Cycle Delay Line, Phase Detector.


  1. Ching-Che Chung, Member and Duo Sheng, A Wide-Range Low-Cost All-Digital Duty Cycle CorrectorIEEE Trans. VeryLarge Scale Integr. (VLSI) Syst., vol. 22, no. 5, pp. 1096–1105,November 11, 2014.
  2. K.-H. Cheng, C.-W.Su, and K.-F. Chang, A high linearity, fastlocking pulsewidth control loop with digitally programmable duty cycle correction for wide range operation, IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 399–413, Feb. 2008.
  3. C.-C. Chung, D. Sheng, and S.-E.Shen, High-resolution all-digital duty-cycle corrector in 65-nm CMOS technology, IEEE Trans. VeryLarge Scale Integr. (VLSI) Syst., vol. 22, no. 5, pp. 1096–1105,May 2014.
  4. Y.-M. Wang and J.-S.Wang, An all-digital 50% duty-cycle corrector,in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2004,pp. II-925–II-928.
  5. H.-J. Hsu, C.-C.Tu, and S.-Y. Huang, A high-resolution all-digitalphase-locked loop with its application to built-in speed gradingfor memory, in Proc. IEEE Int. Symp. VLSI Design, Autom.,Test (VLSI-DAT), Apr. 2008, pp. 267–270.
  6. J. Gu, J. Wu, D. Gu, M. Zhang, and L. Shi, All-digital wide range precharge logic 50% duty cycle corrector,IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 4, pp. 760–764, Apr. 2012.
  7. Y.-M. Wang and J.-S.Wang, An all-digital 50% duty-cycle corrector, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2004, pp. II-925–II-928.
  8. S.-K. Kao and S.-I. Liu, All-digital fast-locked synchronous duty-cycle corrector, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 12, pp. 1363–1367, Dec. 2006.