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Improved architecture for floating-point four-term dot product unit

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Abstract:
This paper presents an improved architecture for floating-point four-term dot product unit.The proposed design work as a unique single unit for floating-point arithmetic to achieve better performance and accuracy.The fixed point number system is not sufficient to handle some complex computations. In contrast, the floating point operations require complex processing increases the area, power consumption and latency.The dot product unit is widely used in digital signal processing (DSP), multimedia, graphics and statistical applications. The improved architecture have multiplier architectures for four terms separately and it have normalization, rounding and detecting-one logic.The proposed design is implemented for single precision and synthesized in Cadence design suite.In order to evaluate the improvement of the proposed design, the area, latency, and power consumption are investigated.The proposed design reduces the area, power consumption and latency compared to traditional design.
Keywords:Digital Signal Processing (DSP), Floating-Point Arithmetic,Dot-Product Unit.

References:

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